DM9301F product brief 100mbps ethernet fiber/twisted pair single chip media converter june 2008 rev.1.0 the dm9301 is a physical-layer, singl e-chip, low-power media converter for 100base-tx/fx full duplex repeater applica tions. on the tx media side, it provides a direct interface to unshielded twisted pair cable 5 (utp5) for 100base-tx fast ethernet. on the fx media side, it provides a direct interface to a pseudo emitter coupled logic level interface (pecl). the dm9301 uses a low power and high perfor mance cmos process. it contains the entire physical layer functions of 100b ase-tx as defined by ieee802.3u, including the physical coding sublayer (pcs), phys ical medium attachment (pma), twisted pair physical medium dependent subl ayer (tp-pmd) and a pecl compliant interface for a fiber optic module, compliant with ansi x3.166. the dm9301 provides two independent clock recovery ci rcuits to minimize bit delay through the converter (no fifo are used to buffer da ta between the fx and tx interfaces). furthermore, due to the excellent rise/f all time control by a built-in wave-shaping filter, the dm9301 needs no exte rnal filter to transport signals to the media on the 100base-tx interface. patent-pending circuits: smart adaptive receiver equalizer ? digital algorithm for high freque ncy clock/data recovery circuit ? high speed wave-shaping circuit block diagram tx code- group alignment monitor descrambler serial to parallel nrzi to nrz rx crm mlt-3 to nrzi adaptive eq cgm 125m tprxclk 25m tprxclk 25m osc/xtal tprxi+/- parallel to serial fx code- group alignment monitor serial to parallel rx crm scrambler parallel to serial nrz to nrzi nrzi to mlt-3 mlt-3 driver tptxo+/- rise/fall time ctl 25m fxrxclk 125m fxrxclk pecl txmt pecl rcvr peclrxi +/- pecltxo +/- fxsd rcvr link status monitor & led driver peclsd nrz to nrzi nrzi to nrz
specifications ? 100base-tx/fx single-chip media converter ? total bit delay from fx to tx interface is 20 bit times (10 bit times each direction). ? optional propagate halt on no link condition ? compliant with ieee802.3u 100base-tx standard, compliant with ansi x3t12 tp-pmd 1995 standard, compliant with ansi x3.166 fddi-pmd ? supports half and full duplex operation 100mbps, the dm9301 operates in full duplex mode at all times ? high performance 100mbps clock generator and data recovery circuit ? controlled output edge rates in the 100base-tx tr ansmitter without the need for an external filter ? led support for fx link, tx link, fx receive data, tx receive data, fx code group error and tx code group error. ? built in led test, all led will light during a reset condition on the dm9301 ? digital clock recovery and regeneration circuit using an advanced digital algorithm to minimize jitter ? supports diagnostic tx to tx analog loopback and fx to fx analog loopback (loopback at the nrzi interface) ? supports diagnostic tx to tx digital loopback and fx to fx digital loopback (loopback at the 5b symbol interface) ? low-power, high-performance cmos process available in a 100 qfp package application 1-to-1 100m fiber converter fiber ip stb, ipc, internet radio ordering information part number pin count package DM9301F 100 qfp davicom semiconductor, inc. no.6, li-hsin rd.vi, science pa rk, hsin-chu, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5646929 e-mail: sales@davicom.com.tw
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